1. Field of the Invention
The present invention relates to an input bias circuit for a charge transfer device (CTD) and is employed in the input section of a delay line, a comb filter, a transversal filter, or the like.
2. Description of the Related Art
An input bias circuit which is made up of a gate input type (i.e., fill & spill type) charge coupled device (CCD) register and an inversion type amplifier has been well known in the art as a circuit for bias-controlling the input charge of a charge transfer device (CTD). The fill & spill type CCD register is described, for example, in Carlo H. Sequin and Michael F. Tompsett, Charge Transfer Devices, Bell Telephone Laboratories, Inc., 1975.
The conventional input bias circuit made up of both the CCD register and the inversion type amplifier has the circuit configuration below.
The CCD register of the input bias circuit is comprised of: an input diode constituted by a diffusion region formed in the substrate; an input gate electrode which is formed on the substrate, with an insulating film interposed, and which is located adjacent to the input diode; a plurality of transfer gate electrodes which are formed on the substrate, with an insulating film interposed, and which are located adjacent to the input gate electrode; a floating diffusion region which is formed on those portions of the substrate surface which are between the transfer gate electrodes and which is used for picking up a transfer charge; and an output diode constituted by a diffusion region which is formed in the substrate and located near the end of arrangement of transfer gate electrodes.
The output terminal of the inversion-type amplifier is connected to the input gate electrode of the CCD register, and the input terminal thereof is connected to the floating diffusion region of the CCD register. An input signal is supplied to the input gate electrode of the CCD register by way of a level-sifting resistor. At the time, a potential well determined in accordance with the input signal is generated in that portion of the substrate which is located under the input gate electrode, and the charge injected from the input diode flows into the potential well. Upon application of a transfer pulse to the transfer gate electrode, the potential well moves to the substrate surface portion which is located under the transfer gate electrode, thus transferring the charge. In the floating diffusion region, charge inflow and charge outflow occur alternately. The difference between the output charge SO picked up in the floating diffusion region and the input charge QI injected from the input diode is integrated in accordance with capacitance CFD, thereby determining voltage VFD to be applied to the inversion-type amplifier. In response to the application of voltage VFD, inversion-type amplifier outputs voltage VIB, which is used for biasing the input signal supplied through the level-shifting resistor. Voltage VFD is determined by the following formula: ##EQU1##
As is understood from this formula, if QO&gt;QI, voltage VFD is high. In this case, the inversion-type amplifier lowers voltage VIB, so that the input charge QI increases. On the other hand, if QO&lt;QI, voltage VFD is low. In this case, the inversion-type amplifier raises voltage VIB, so that the input charge QI decreases. Therefore, the condition for producing a stable state is represented by QI=QO, and when this relationship is satisfied, voltage VIB is stable.
A signal charge biased by the bias circuit mentioned above is transferred through a CCD delay line. Let it be assumed that the maximum transferable charge amount of the CCD delay line is denoted by Qa and that the channel width of that CCD delay line is denoted by Wa. If the CCD delay line and the input section of the CCD register are the same in shape and if the charge amount which can be input is sufficiently larger than the maximum transferable charge amount Qa, the maximum transferable charge amount changes in proportion to the channel width Wa. Further, since the output charge QO of the CCD register corresponds to the maximum transferable charge amount of the charge-expelling channel located behind the floating diffusion region, it changes in proportion to the width WO of the charge-expelling channel. Therefore, the following formula is obtained: EQU Qa:QO=Wa:WO (2)
As may be understood from this formula, the charge accounting for a certain percentage of the maximum transferable charge amount of the CCD delay line can be supplied to the CCD register by properly determining the channel width WO. The voltage VIB applied when that charge is injected into the CCD register is the same as the voltage applied when the CCD delay line receives a certain percentage of charge, and with the voltage VIB being used as an input bias of the CCD delay line, the bias voltage can be determined at a level corresponding to an arbitrary percent of the maximum transferable charge amount. Even if the CCD does not have such characteristic as intended at the time of design, optimal biasing is always achieved since the bias voltage is determined at the level noted above.
The input bias circuit described above has such a problem to be discussed below.
In a system incorporating the above input bias circuit, it may happen that voltage VIB will lower when the system is turned on or in some other situation. At such a time, the potential applied to the input gate electrode will lower. If this potential becomes lower than the low-level (L-level) potential applied to the input diode, no charge is injected into the CCD register. In the input bias circuit, therefore, the potential applied to the input gate electrode is maintained within the range between the high-level (H-level) and the low-level (L-level) of the potential applied to the input diode, so as to control the injection of the input charge QI. However, if the well whose potential is applied to the input gate electrode is shallower than the well whose potential is applied to the input diode, then it becomes impossible to inject charge. Since, therefore, no charge is transferred to the floating diffusion region, voltage VFD rises. If voltage VFD rises, voltage VIB (i.e., the output of the inversion-type amplifier) further lowers, and the potential at the input gate electrode to which voltage VIB is applied is undesirably maintained at a lower level than that of the L-level potential applied to the input diode, with the result that an input bias voltage is not generated.
To solve the problem mentioned above, it is thought to add a potential level-controlling function to a control pulse generator which generates pulses for controlling the injection, transfer and output of charge. In other words, voltage VIB is detected, and control is performed such that the L-level potential applied to the input diode is constantly maintained at a level lower than that of the potential applied to the input gate electrode. However, the control pulse generator having such a function cannot be operated at high speed when it is operated on a low power source voltage, and is not suitable for use with a CCD register which requires high-speed operation when operated on a low voltage.
As mentioned above, the conventional input bias circuit does not permit charge to be injected into the CCD register if voltage VIB becomes low when the power source is turned on or in some other situation. In the worst case, the conventional input bias circuit cannot generate an input bias voltage. Even if the control pulse generator of the input bias circuit is designed to have a potential level-controlling function, the input bias circuit is not suitable for use with a CCD register which requires a high-speed operation at the time of application of a low voltage.